1. Field of the Invention
This invention relates to a bipolar semiconductor integrated circuit device and a process of manufacturing the same, and more particularly to the structure of an NPN bipolar transistor and a process of manufacturing the same.
2. Description of the Prior Art
Conventionally, the high speed operation and high driving capacity of a bipolar transistor is achieved by two methods.
According to the first method, parasitic resistances of electrodes and diffused layers of an emitter, base and collector and parasitic capacitances between the electrodes and at junctions of diffused layers of the emitter, base and collector are minimized.
According to the second method, a cut-off frequency fT is improved. The second method is achieved by reducing the depth of the base diffused layer to reduce the base width and improve the cut-off frequency fT, or by providing, for example, in an NPN bipolar transistor, an N-type impurity area having an impurity concentration higher than the impurity concentration of an N-type epitaxial layer or an N-type well region present between a P-type intrinsic base region and an N.sup.+ buried layer region of the collector but lower than the impurity concentration of the N+ buried layer to control the Kirk effect to improve the cut-off frequency of the bipolar transistor.
In those methods, bipolar transistors are normally used in pairs in order to achieve high speed operation and high driving capacity of a bipolar transistor.
For example, in a process of manufacturing a bipolar transistor disclosed in JP,A, 2-215158, in the first method polycrystalline silicon worked to a small width is used as an emitter electrode to achieve reduction in magnitude of electrodes of a bipolar transistor in a transverse direction to reduce the resistance and the capacitance parasitic in the bipolar transistor itself.
Next, in the second method, Using a mask such as mask 11 as shown in FIG. 3(a), an N-type impurity region 6 is provided over the entire range just below intrinsic base region 7 and extrinsic base region 10 between N.sup.+ -type buried layer region 2 and intrinsic base region 7 to control a depletion layer between the base and the collector from extending to the collector side thereby to achieve improvement of the cut-off frequency fT which is one of the AC characteristics of a bipolar transistor.
Next, the process of manufacturing a bipolar transistor of the conventional structure disclosed in JP,A, 2-215158 is described with reference to the drawings. FIGS. 1 and 2 are sectional views of a semiconductor element illustrating the process of manufacturing a bipolar transistor of the conventional structure.
The process of manufacturing a bipolar transistor of the conventional structure is described below with reference to FIGS. 1 and 2.
Referring to FIG. 1, N.sup.+ -type buried layer region 2 and an N-type epitaxial layer are formed on P-type semiconductor substrate 1, and then the N-type epitaxial layer is changed into N-type well region 4 by ion implantation. Further, device separating oxide (insulation) film 5 is formed, and then, N-type impurity region 6 and intrinsic base region 7 are formed in desired regions by ion implantation using mask 11.
Thereafter, in FIG. 2, emitter electrode 8 is formed on the article shown in FIG. 1, and oxide film spacer 9 is formed using a known CVD (Chemical Vapour Deposition) technique and a known anisotropic etching technique, whereafter extrinsic base region 10 is formed by ion implantation.
In the bipolar transistor of the conventional structure described above, however, since an N-type impurity region is formed using mask 11 for formation of an intrinsic base region having an opening of a large area as shown in FIG. 3(a) and FIG. 3(b) which shows a cross section taken along line A--A of FIG. 3(a), N-type impurity region 6 having a concentration higher than that of N-type well region 4 is present over the overall area just below intrinsic base region 7 and extrinsic base region 10 as shown in the sectional view of FIG. 3(b). Consequently, a high capacitance occurs between the collector and the base and this is one of the causes of the slow circuit operation of the bipolar transistor.
The inventor of the present invention conducted an experiment and simulation to determine a relationship of the capacitance C.sub.BC between the base and the collector and the cut-off frequency fT to the distance from emitter slit 12 to N-type impurity region 6. The result of the experiment and simulation proved that, as shown in FIGS. 4 and 5, even if distance X from emitter slit 12 to N-type impurity region 6 is X&gt;0.5 .mu.m, the capacitance C.sub.BC between the base and the collector continues to increase and the cut-off frequency fT is not improved.